1 idt74fct163344a/c 3.3v cmos one-to-four address/clock driver industrial temperature range january 2004 industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. ? 2004 integrated device technology, inc. dsc-3249/3 features: ? 0.5 micron cmos technology ? typical t sk(o) (output skew) < 250ps ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ?v cc = 3.3v 0.3v, normal range, or v cc = 2.7v to 3.6v, extended range ? cmos power levels (0.4 w typ. static) ? rail-to-rail output swing for increased noise margin ? low ground bounce (0.3v typ.) ? inputs (except i/o) can be driven by 3.3v or 5v components ? available in ssop and tssop packages functional block diagram idt74fct163344a/c 3.3v cmos one-to-four address/clock driver description: the fct163344 is a 1:4 address/clock driver built using advanced dual metal cmos technology. this high-speed, low power device provides the ability to fanout to memory arrays. eight banks, each with a fanout of 4, and 3-state control provide efficient address distribution. one or more banks may be used for clock distribution. the fct163344 has series current limiting resistors. these offer low ground bounce, minimal undershoot and controlled output fall times, reducing the need for external series terminating resistors. a large number of power and ground pins ensure reduced noise levels. all inputs are designed with hysteresis for improved noise margins. the inputs of the fct163344 can be driven from either 3.3v or 5v device. this feature allows the use of these devices as translators in a mixed 3.3v/ 5v supply system. a 1 a 2 b 11 oe 1 b 14 b 21 b 24 a 3 a 4 b 31 oe 2 b 34 b 41 b 44 a 7 a 8 b 71 oe 4 b 74 b 81 b 84 a 5 a 6 b 51 oe 3 b 54 b 61 b 64 1 8 14 2 6 9 13 28 15 21 16 20 23 27 43 49 56 48 44 55 51 29 36 42 34 30 41 37
2 industrial temperature range idt74fct163344a/c 3.3v cmos one-to-four address/clock driver oe1 b 11 b 12 gnd b 13 b 14 v cc a 1 b 21 b 22 gnd b 23 b 24 a 2 b 32 b 42 a 3 gnd b 33 a 4 v cc b 41 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 49 50 51 52 53 54 55 56 1 oe4 b 81 b 82 b 72 b 83 b 84 v cc a 8 b 71 gnd b 73 b 74 a 6 b 61 b 62 b 63 b 64 a 5 v cc b 51 b 31 gnd a 7 gnd gnd b 43 25 26 27 28 32 31 30 29 gnd b 53 b 54 oe 3 b 44 b 52 oe 2 b 34 pin configuration symbol description max unit v term (2) terminal voltage with respect to gnd ?0.5 to +4.6 v v term (3) terminal voltage with respect to gnd ?0.5 to 7 v v term (4) terminal voltage with respect to gnd ?0.5 to v cc +0.5 v t stg storage temperature ?65 to +150 c i out dc output current ?60 to +60 ma absolute maximum ratings (1) (1) (1) (1) (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. vcc terminals. 3. input terminals. 4. outputs and i/o terminals. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 3.5 6 pf c out output capacitance v out = 0v 3.5 7 pf capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is measured at characterization but not tested. ssop/ tssop top view pin description pin names description oe x 3-state output enable inputs (active low) a x inputs b x x 3-state outputs note: 1. h = high voltage level l = low voltage level x = don't care z = high-impedance function table (1) inputs outputs oe x ax bxx ll l lh h hx z
3 idt74fct163344a/c 3.3v cmos one-to-four address/clock driver industrial temperature range symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level (input pins) guaranteed logic high level 2 ? 5.5 v input high level (i/o pins) 2 ? v cc +0.5 v il input low level (input and i/o pins) guaranteed logic low level ?0.5 ? 0.8 v i ih input high current (input pins) v cc = max. v i = 5.5v ? ? 1 input high current (i/o pins) v i = v cc ?? 1a i il input low current (input pins) v i = gnd ? ? 1 input low current (i/o pins) v i = gnd ? ? 1 i ozh high impedance output current v cc = max. v o = v cc ?? 1a i ozl (3-state output pins) v o = gnd ? ? 1 v ik clamp diode voltage v cc = min., i in = ?18ma ? ?0.7 ?1.2 v i odh output high current v cc = 3.3v, v in = v ih or v il, v o = 1.5v (3) ?36 ?60 ?110 ma i odl output low current v cc = 3.3v, v in = v ih or v il, v o = 1.5v (3) 50 90 200 m a v oh output high voltage v cc = min. i oh = ?0.1ma v cc -0.2 ? ? v in = v ih or v il i oh = ?3ma 2.4 3 ? v v cc = 3v i oh = ?8ma 2.4 (5) 3? v in = v ih or v il v ol output low voltage v cc = min. i ol = 0.1ma ? ? 0.2 v in = v ih or v il i ol = 16ma ? 0.2 0.4 i ol = 24ma ? 0.3 0.55 v v cc = 3v i ol = 24ma ? 0.3 0.5 v in = v ih or v il i os short circuit current (4) v cc = max., v o = gnd (3) ?60 ?135 ?240 ma v h input hysteresis ? ? 150 ? mv i ccl quiescent power supply current v cc = max. ? 0.1 10 a i cch v in = gnd or v cc i ccz dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = ?40c to +85c, v cc = 2.7v to 3.6v notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 3.3v, +25c ambient. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. this parameter is guaranteed but not tested. 5. v oh = v cc ?0.6v at rated current.
4 industrial temperature range idt74fct163344a/c 3.3v cmos one-to-four address/clock driver symbol parameter test conditions (1) min. typ. (2) max. unit ? i cc quiescent power supply current v cc = max. ? 2 30 a ttl inputs high v in = v cc - 0.6v (3) i ccd dynamic power supply v cc = max. v in = v cc ? 230 320 a/ current (4) outputs open v in = gnd mhz oe x = gnd one input bit togging four output bits togging 50% duty cycle i c total power supply current (6) v cc = max.,outputs open v in = v cc ? 2.3 3.2 ma f i = 10mhz v in = gnd 50% duty cycle oe x = gnd v in = v cc - 0.6v ? 2.3 3.2 one input bit toggling v in = gnd four output bits togging v cc = max.,outputs open v in = v cc ? 4.6 6.4 (5) f i = 2.5mhz v in = gnd 50% duty cycle oe x = gnd v in = v cc - 0.6v ? 4.6 6.5 (5) eight input bits toggling v in = gnd 32 output bits togging power supply characteristics notes: 1. for conditions shown as min. or max., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 3.3v, +25c ambient. 3. per ttl driven input. all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + ? i cc d h n t + i ccd (f cp n cp /2 + fini) i cc = quiescent current (i ccl , i cch and i ccz ) ? i cc = power supply current for a ttl high input d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) n cp = number of clock inputs at f cp fi = input frequency ni = number of inputs at fi
5 idt74fct163344a/c 3.3v cmos one-to-four address/clock driver industrial temperature range fct163344a fct163344c symbol parameter condition (2) min. (3) max. min. (3) max. unit t plh propagation delay c l = 50pf 1.5 4.8 1.5 4.3 ns t phl ax to bxx r l = 500 ? t pzh output enable time 1.5 6.2 1.5 5.8 ns t pzl oe x to bxx t phz output disable time 1.5 5.6 1.5 5.2 ns t plz oe x to bxx t sk(b) skew between outputs of the same bank and ? 0.5 ? 0.35 ns same package (same transition) (4,5) t sk(o) skew between outputs of all banks of the same ? 0.5 ? 0.5 ns package (a1 - a8 tied together) (4,5) switching characteristics over operating range (1) notes: 1. propagation delays and enable/disable times are with v cc = 3.3v 0.3v, normal range. for v cc = 2.7v to 3.6v, extended range, all propagation delays and enable/disable times should be degraded by 20%. 2. see test circuit and waveforms. 3. minimum limits are guaranteed but not tested on propagation delays. 4. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design. 5. this parameter is guaranteed but not tested. skew is not guaranteed when v cc < 0.3v.
6 industrial temperature range idt74fct163344a/c 3.3v cmos one-to-four address/clock driver pulse generator r t d.u.t. v cc v in c l v out 50pf 500 ? 500 ? open gnd 6v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input preset clear etc. t su t h t rem t su t h preset clear clock enable etc. high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v o l control input 3v 1.5v 0v 3v 0v output normally low output normally high switch 6v switch gnd v ol 0.3v 0.3v t plz t pz l t pzh t phz 3v 0v 1.5v 1.5v enable disable v oh t plh1 output 1 output 2 t sk(x) t plh2 v ih 0v v oh v t v t v ol v oh v t v ol input t phl1 t phl2 t sk(x) t sk(x) = |t plh2 - t plh1 | or |t phl2 - t phl1 | test circuits and waveforms propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times pulse width test switch open drain disable low 6v enable low disable high gnd enable high all other tests open switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. 3. if v cc is below 3v, input voltage swings should be adjusted not to exceed v cc . output skew - t sk ( x ) notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank.
7 idt74fct163344a/c 3.3v cmos one-to-four address/clock driver industrial temperature range idt xx xxx xx package device type temp. range pv pa 163 74 shrink small outline package thin shrink small outline package one-to-four address/clock driver -40c to +85c xxx family 344a 344c double-density 3.3v fct ordering information corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com 4/22/2002 removed blank speed grade data sheet document history
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